Memory Architecture Exploration For Programmable Embedded by Grinn, Dutt, Nicolau

By Grinn, Dutt, Nicolau

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By traversing the most active basic blocks, we extract the most active access patterns from the application. 3 shows an excerpt of code from compress, containing references to 3 arrays: htab, codetab, and rmask. htab is a hashing table represented as an array of 69001 unsigned longs (we assume that both longs and ints are stored using 32 bits), codetab is an array of 69001 shorts, and rmask is an array of 9 characters. The sequence of accesses to htab, codetab, and rmask represent access patterns ap1, ap2 and ap3 respectively.

The adder computes the address for the next data element based on the base address and the previous data value. We assume that the base register is initialized to the base of the codetab array and the index register to the initial index through a memory mapped control register model (a store to the address corresponding to the base register writes the base address value into the register). The custom memory modules from the library can be combined together, based on the relationships between the access patterns.

The first column shows the application, and the second column represents the memory architectures explored for each such benchmark. The third column represents the cost of the memory architecture (in number of basic gates), the fourth column represents the miss ratio for each such design point, the fifth column shows the 2 Not all exploration points (X) are covered by a full simulation point (black dot), since some of the exploration points represent estimations only 44 MEMORY ARCHITECTURE EXPLORATION average memory latency (in cycles), and the last column presents the average memory power consumption, normalized to the initial cache-only architecture (represented by the first design point for each benchmark).

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