Coupled Data Communication Techniques for High-Performance by Dr. Ron Ho, Dr. Robert Drost (auth.), Ron Ho, Robert Drost

By Dr. Ron Ho, Dr. Robert Drost (auth.), Ron Ho, Robert Drost (eds.)

Designers of next-generation high-performance computers face a bunch of technical demanding situations. For the earlier numerous many years, emerging clock frequencies and elevated chip integration have fueled the expansion of desktop functionality. Now those tendencies have slowed: strength and complexity constrains additional raises in clock frequencies, and fiscal realities restrict the velocity of Moore's legislations. Coupled information conversation presents a manner ahead, and this booklet, Coupled info verbal exchange thoughts for High-Performance and Low-Power Computing, provides a accomplished evaluate for such coupled info concepts. Coupled facts conversation permits chips to communicate—capacitively or inductively—over brief distances among chips with out solder, and essentially shifts the layout paradigm from single-chip integration to single-package integration. This booklet covers the state of the art within the circuits, architectures, and chip packaging for this novel chip-to-chip communique expertise and showcases its capability to force the arriving many years of development. Coupled facts conversation options for High-Performance and Low-Power Computing may be of curiosity to scholars and architects in circuits and approach architecture.

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Each silicon die in the 3D stack contains the following features: 1) a monolithically integrated microchannel heat sink; 2) through-silicon electrical (copper) vias (TSEVs) and through-silicon fluidic (hollow) vias (TSFVs); 3) solder bumps (electrical I/Os) and microscale polymer pipes (fluidic I/Os) on the side of the chip opposite to the microchannel heat sink. Microscale fluidic interconnection between strata is enabled by the combination of through-wafer fluidic vias and polymer pipe I/O interconnects.

2007 IEEE Fig. 28 On-chip power/ground grids and I/O pads in flip-chip technology. Different types of modeling methods can be used to analyze power supply noise, such as circuit simulation methods, 3D electromagnetic solver methods, and compact physical models. Circuit simulations and 3D solvers are commonly used for 2 2D and 3D integrated systems 35 dedicated validation after designs are fulfilled. However, to gain sufficient physical insight, compact and accurate physical models are needed before the physical designs are performed.

The first droop is caused by the package inductance and ondie capacitance. The resonance frequency of the first droop is in the range of tens of MHz to a few hundred of MHz depending on the sizes of package level components and on-chip decaps [47]. Because putting additional on-chip decaps is very costly, among the three droops, the first droop is the most difficult one to suppress. The first droop noise has the largest magnitude. Even though the first droop has the smallest time of occurrence it can adversely affect GSI circuits as its duration can be tens of nano seconds (ns).

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