A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph relies at the 3rd author's lectures on desktop structure, given in the summertime semester 2013 at Saarland collage, Germany. It incorporates a gate point development of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.

The booklet includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence. This opens the best way to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the improvement of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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R ∈ Bn . R = Rin(ht ) Rce(ht ) = 1 Rce(ht ) = 0 . R ∈ Bn . 5 Drivers and Main Memory 55 yin yin α OC y y α β β Fig. 27. Open collector driver and its timing diagram collector drivers, and main memory. 5 that a design that works in the digital model also works in the detailed hardware model. For tristate drivers and main memory this will not be the case. 1 Open Collector Drivers and Active Low Signal A single open collector driver y and its detailed timing is shown in Fig. 27. If the input yin is 0, then the open collector driver also outputs 0.

Here, all input signals are binary and stable for the maximal propagation delay β before t. For inverters y this is captured by the following predicate: reg(y, t) ↔ ∃a ∈ B : ∀t ∈ [t − β, t] : in1(y)(t ) = a . Gate y in this case outputs a at time t. For ◦-gates y we define reg(y, t) ↔ ∃a, b ∈ B : ∀t ∈ [t − β, t] : in1(y)(t ) = a ∧ in2(y)(t ) = b . Then gate y outputs a ◦ b at time t. 48 3 Hardware in1 in2 β α y t2 − β t − α t1 t2 t Fig. 23. 4 • Signal holding. Here, signal propagation is not regular anymore but it was regular at some time during the minimal propagation delay α before t: hold(y, t) ↔ ¬reg(y, t) ∧ ∃t ∈ [t − α, t] : reg(y, t ) .

An n-bit register R consists simply of n many 1-bit registers R[i] with a common clock enable signal Rce as shown in Fig. 26. R ∈ Bn . R = Rin(ht ) Rce(ht ) = 1 Rce(ht ) = 0 . R ∈ Bn . 5 Drivers and Main Memory 55 yin yin α OC y y α β β Fig. 27. Open collector driver and its timing diagram collector drivers, and main memory. 5 that a design that works in the digital model also works in the detailed hardware model. For tristate drivers and main memory this will not be the case. 1 Open Collector Drivers and Active Low Signal A single open collector driver y and its detailed timing is shown in Fig.

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